Low Density Parity Check (LDPC) codes have recently attracted considerable attention owing to their capacity-approaching performance and low complexity iterative decoding. LDPC codes can be applied to a wide range of applications such as wireless communications, satellite communications and storage.
An example wireless system is a 802.11n communication. FIG. 1 shows a functional block diagram of a conventional transmitter 100. The user information bits are encoded using a short to moderate block length Low Density Parity Check (LDPC) code in an LDPC Encoder 102. The encoded bits then pass through a bit-by-bit round robin Spatial Parser 104, followed by the usual Constellation Mapper 106, and OFDM modulation including Inverse FFT 108, Guard Interval (GI) Window 110 and RF modulation windowing 112. In such a transmitter 100, the decoding data rates must be over 100 Mbps, which are not favorable for turbo coding. LDPC codes, which are designed for parallel implementation, provide a good alternative for satisfying stringent requirements in terms of block error rate and decoding throughput.
LDPC code is a type of linear block coding and can be uniquely defined by a parity check matrix H. The code rate is R=M/N, where N is the number of columns in the H matrix, representing the size of the code, and M is the number of rows in the H matrix, representing the number of parity check equations. An example of a linear block code with N=7, M=3, is shown in relation (1) below:
                    H        =                  [                                                    1                                            0                                            1                                            0                                            1                                            0                                            1                                                                    0                                            1                                            1                                            0                                            0                                            1                                            1                                                                    0                                            0                                            0                                            1                                            1                                            1                                            1                                              ]                                    (        1        )            
LDPC codes can be effectively represented using a bipartite graph. The nodes in the graph are separated into two distinctive sets and edges are only connecting nodes of two different types. The two types of nodes in the bipartite graph are called bits nodes and check nodes. One bit node represents one bit in the codeword, corresponding to one column of the parity check matrix H. One check node represents one parity check equation, corresponding to one row of the parity check matrix H. FIG. 2 shows a graph representation 200 of the (7,4) parity check codes given in relation (1) above. In the graph 200 of FIG. 2, an open circle (∘) represents the bit node, and a solid square (▪) represents the check node.
LDPC codes can be efficiently decoded using a message-passing algorithm. Such an algorithm operates on the bipartite graph by iteratively updating the soft message. Examples of message-passing algorithms can be found in R. G. Gallager, “Low density parity check codes”, IRE Trans. Inform. Theory, Vol. IT-8, pp. 21-28, January 1962, and in D. J. C. MacKay and R. M. Neal, “Neal Shannon limit performance of low density parity check codes,” Electronics Letters, vol. 32, pp. 1645-1646, 1996.
There are two kinds of LDPC codes, regular and irregular. A regular LDPC code contains t number of 1's per-row (row weight) and s number of 1's per column (column weight), where s=t*(1−R). An irregular LDPC code contains uneven number of 1's per-column and per-row. For example, the H matrix in relation (1) is an irregular code. It has been known that irregular LDPC codes outperform regular LDPC codes and have decoding thresholds very close to Shannon capacity. Design of good irregular code ensemble for randomly generated codes is presented in T. J. Richardson, M. A. Shokrollahi and R. L Urbanke, “Design of capacity-approaching irregular low-density parity-check codes”, IEEE Transactions on Information Theory, Volume: 47, Issue: 2, February 2001, Pages: 619-637. A general technical called density evolution is proposed to find the best code weight distribution which provides the best code ensemble. This weight distribution provides design guideline for infinite size LDPC codes. The effectiveness of the design is verified by randomly generated large LDPC codes.
Although randomly generated long LDPC codes (over 10K size) have threshold-approaching performance, the design of short codes with reasonably good performance has been a challenge. Furthermore, the design of LDPC codes that are fit for hardware implementation such as ASIC is very important, especially for 802.11n systems where the decoding throughput is required to be over 100 Mbps. Therefore, some conventional approaches introduce code structure in the LDPC code design to facilitate hardware implementation. For example, a block structured regular LDPC code design and the corresponding FPGA prototyping is presented in “H. Zhong and T. Zhang, “Block-LDPC: A Practical LDPC Coding System Design Approach”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Volume 52, Issue 4, April 2005 Page (s) 766-775. However, the performance of such regular codes is below that of irregular codes.